1. Field of the Invention
The present invention relates to a semiconductor device suitably applied to a semiconductor device including a DRAM (Dynamic Random Access Memory) with a COB (Capacitor Over Bit-line) structure in which a capacitor is arranged on a layer above a bit line, and a method of manufacturing the same.
2. Description of the Prior Art
With the advance of micropatterning of DRAM memory cells, it is becoming increasingly difficult to obtain sufficient storage capacitance. Accordingly, a COB structure in which a capacitor is formed above a bit line is widely used because the entire surface area of the capacitor can be made large. In the DRAM of the COB structure, a contact hole for connecting a node electrode as one electrode of the capacitor and an element active region is formed from a layer above a contact hole for connecting the bit line and the element active region. For this reason, with the advance of micropatterning of DRAM memory cells, the aspect ratio of the contact hole for connecting the node electrode and the element active region greatly increases, and a conductive material is difficult to bury in the contact hole. As a result, an error easily occurs at the contact hole.
As a method for solving this problem, the following technique is proposed. According to this technique, when a contact hole for connecting a bit line and an element active region is formed in a lower insulating interlayer, a contact hole for connecting a node electrode and the element active region is simultaneously formed. A pad is formed in the contact hole using a conductive layer connected to the element active region. A contact hole is again formed in an upper insulating interlayer. The node electrode is connected to the pad via this contact hole. Such technique will be described below.
FIGS. 1A to 1G are sectional views respectively showing the steps in a method of manufacturing a semiconductor device as the first prior art. First, as shown in FIG. 1A, a field oxide film 2 is formed on a p.sup.- -type semiconductor substrate 1 by a normal LOCOS process. A gate oxide film 3 is formed on an element active region partitioned by the field oxide film 2. A conductive film such as a polysilicon film or a tungsten silicide film is grown to a film thickness of about 200 nm on the entire surface and patterned into a predetermined shape to form word lines 5. An impurity is doped in the semiconductor substrate 1 to form source/drain regions 4, thereby forming a MOS transistor using the word line 5 as a gate electrode. Thereafter, a first insulating interlayer 7 such as a silicon oxide film doped with an impurity, e.g., phosphorus or boron is grown to a film thickness of about 300 nm on the entire surface.
As shown in FIG. 1B, the resist pattern of a contact hole 9a for connecting a bit line (not shown) and the element active region and that of a contact hole 9b for connecting a storage node electrode (not shown) and the element active region are simultaneously formed by normal lithography. After isotropic etching is slightly performed using the resist patterns as a mask, anisotropic etching is performed to form contact holes each tapered wider in the upward direction. As shown in FIG. 1C, e.g., a polysilicon film doped with an impurity such as phosphorus is grown to a film thickness of about 600 nm on the entire surface, and is etched back to form a first buried conductive layer 11 as a pad in each contact hole.
As shown in FIG. 1D, for example, a conductive layer such as a tungsten silicide film is grown to a film thickness of about 150 nm on the entire surface and patterned into a predetermined shape to form a bit line 12. As shown in FIG. 1E, for example, a second insulating interlayer 14, such as a silicon oxide film doped with an impurity, e.g., phosphorus or boron, having a film thickness of about 300 nm is formed on the entire surface.
Subsequently, as shown in FIG. 1F, a contact hole 18 is formed in a layer above the first buried conductive layer 11 which is formed in FIG. 1C and buried in the contact hole 9b for connecting the node electrode and the element active region. As shown in FIG. 1G, a polysilicon film doped with an impurity such as phosphorus is grown to a film thickness of about 600 nm on the entire surface and then patterned into a predetermined shape to form a storage node electrode 17. If the storage node electrode 17 is formed to have a three-dimensional structure such as a fin shape or a cylinder shape, the storage capacitance can be further increased.
In the first prior art, even when a contact hole having a larger aspect ratio is to be formed, a plurality of contact holes can be stacked. For this reason, the depth of the contact hole on each stage can be made small. Compared to a case wherein a contact hole is formed from an upper layer in only one stage, it becomes possible to prevent the formation of an incomplete conact hole.
In the first prior art, however, a sufficient margin cannot be assured in forming the contact hole 18 or the second stage above the contact hole 9b on the first stage. That is, in this technique, since the upper portion of the contact hole 9b is tapered wider by isotropic etching, the pad 11 having a diameter larger than that of the contact hole formed in advance is formed at this upper portion. The tapering size to which the upper portion can be widened depends on the film thickness of the contact hole 9b on the first stage. For this reason, to prevent a short circuit between adjacent pads, a thick pad cannot be formed. For example, if the diameter of the contact hole/interval=150 nm/300 nm, the pad film thickness is about 100 nm at most and if the diameter of the contact hole/interval=200 nm/200 nm, the pad film thickness decreases to about 50 nm. In forming a contact hole on the second stage, if the opening is formed at the end of the pad due to misalignment, the pad does not sufficiently serve as a stopper in forming the opening. Consequently, the contact hole on the second stage surface extends through the pad to easily cause errors such as a short circuit between adjacent word lines or reaches the element active region to damage this region.
To solve the problem of misalignment in the first prior art, for example, as shown in FIG. 2, it is only necessary to form a large pad 11A of a conductive layer widened in a mushroom-cap shape above the first insulating interlayer 7 having the pad 11 in the contact hole formed in advance, and to form a contact hole 18 on the second stage so as to contact the upper portion of the large pad 11A. Such technique is disclosed in, e.g., Japanese Unexamined Patent Publication No. 4-5823. According to the second prior art, as shown in FIG. 3A, after a MOS transistor is formed, a first etching stopper insulating film 6, a first insulating interlayer 7, a first buffer layer 21, and a silicon oxide film 22 are sequentially deposited.
Next, as shown in FIG. 3B, normal lithography and etching are performed up to the upper portions of the first etching stopper insulating film 6, thereby forming contact holes 9a and 9b. As shown in FIG. 3C, side walls 23 consisting of second buffer layers 23 are formed inside the formed contact holes, and openings are formed in the first etching stopper insulating film 6 using the first buffer layer 21 and the second buffer layers 23 as a mask.
As shown in FIG. 3D, conductive layers are buried in the contact holes and etched back to form pads 11. After a conductive layer is further deposited on the uppermost layer, a bit line 24a and a contact electrode 24b as a storage node electrode are formed by normal lithography and etching. Finally, as shown in FIG. 3E, side walls consisting of third buffer layers 25 are formed on the side walls of the bit line 24a and the contact electrode 24b, and the first buffer layer 21 is etched using the bit line 24a, the contact electrode 24b, and the third buffer layers 25 as a mask to simultaneously form a bit line 12 and a large pad 11A.
In the second prior art, short circuits easily occur between adjacent pads and between the pad and the bit line. This problem is becoming more serious as memory cells continue to shrink. FIG. 8 is a plan view showing an example of the configuration of memory cells in an open bit line system. In this example, when contact holes 9a each for connecting a bit line 12 and an element active region 4 and contact holes 9b each for connecting a node electrode 17 and the element active region 4 are simultaneously formed, the contact holes 9a, 9b are aligned at equal intervals in such a manner that the diameter of each contact hole and the interval between adjacent pads are at about 1:1. Therefore, in the method of forming a pad formed on the contact hole and having a diameter larger than that of the contact hole, the interval between adjacent pads is very narrow.
As shown in FIG. 2, the bit line 12 and the large pad 11A adjacent thereto are formed at the same level on the first insulating interlayer 7, and the large pad 11A is formed to have a diameter larger than that of the contact hole 9b. Therefore, as shown in the lower right corner of FIG. 8, a portion X susceptible to a short circuit between the pad and the bit line is undesirably formed. Further, since the interconnection and the pad portion are simultaneously formed, lithography is difficult to perform at a portion where the pad is close to the bit line. This method is not suitable for application to micropatterned memory cells.
To suppress the short circuit, Japanese Unexamined Patent Publication No. 3-174766 proposes a modification as shown in FIG. 4. According to this technique, after a large pad 11A is formed on a pad 11, an insulating interlayer 26 between the pad portion and the bit line is formed thereon to have a film thickness of about 100 nm. A bit line 12 is formed after a contact hole 27 for connecting the bit line 12 and the large pad 11A is formed in the insulating interlayer 26. A second insulating interlayer 14 is formed, and a contact hole 18 is formed to form a node electrode 17.
The improved technique described in this publication however, requires a larger number of steps from the step of depositing the insulating interlayer 26 between the pad portion and the bit line to the step of forming the contact hole 27 for connecting the bit line and the pad portion. As a result, the labor and cost required increase.
In addition, steps in a peripheral circuit portion and a memory cell also increase.